10 bit 80 Msample/s流水线ADC的电路级设计  

A 10 bit 80 Msample/s Pipelined ADC

作　　者：郑晓燕[1] 仇玉林[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《电子器件》2007年第5期1819-1821,1825,共4页Chinese Journal of Electron Devices

摘　　要：实现了0.18μmCMOS模拟工艺、1.8V电源电压下10位分辨率、80MHz采样率的流水线ADC的电路级设计,采用栅压自举的采样开关和增益提升运放保证ADC的精度;采用复位结构的SHC和MDAC消除运放失调电压的影响;采用动态比较器并优化每级电容以降低功耗.当输入信号幅度为1Vpp时,ADC在整个量化范围内无失码,当输入信号频率为39MHz时,可获得71.6dB的无失真动态范围和60.56dB的信噪失真比.Circuit level design of a 10 bit 80Msample/s pipelined ADC is realized in a 1.8 V,0.18 μm standard CMOS analog process.Signal dependent clock bootstrapping switch and gain-boost OTA are adopted to ensure the resolution.Resetting SHC and MDAC are used to cancel offset of the OTA.Dynamic comparator and optimization of the sampling capacitor are adopted to reduce power consumption.Simulation results show that when input signal range is 1 Vpp and input signal frequency is 39 MHz,71.6 dB of SFDR and 60.56 dB SIN...

关 键 词：模数转换器 流水线 栅压自举开关 增益提升运放 

分 类 号：TN792[电子电信—电路与系统]