MPEG-4形状编码器二进制运动估计的VLSI结构设计  

VLSI Architecture Design of Binary Motion Estimation in MPEG-4 Shape Codec

作　　者：王占辉[1] 刘大明[1] 

机构地区：[1]海军工程大学电气与信息工程学院,武汉430033

出　　处：《电子器件》2007年第6期2112-2118,共7页Chinese Journal of Electron Devices

摘　　要：阐明了所设计的二进制运动估计的VLSI硬件结构.首先介绍了MPEG-4形状编码中BME的基本原理,以及前人设计的一种DDBME结构;接着分析指出DDBME在利用数据冗余方面的缺陷,并给出了一种改进的运动估计结构,通过扩大PE阵列以及重新安排数据的分发机制,可以达到75%的数据利用率.硬件仿真结果与软件运行结果的对比表明了本设计的正确性,综合结果也说明了本设计可以在最低5.93MHz的频率下满足MPEG-4 Core Profile & Level2的实时编码,可用于MPEG-4的VLSI实现.The VLSI architecture of binary motion estimation is presented.Firstly, the basic theory of BME (binary motion estimation) in MPEG-4 shape coding and the DDBME designed by Chang are introduced. Secondly, the flawing of data redundancy used in DDBME is analyzed and an improved architecture is designed by increasing the PEs and rearranging the mechanism of sending data, so the percentage of using data reaches 75 percent. Finally, the VLSI architecture and implementation in terms of VHDL were designed in the X...

关 键 词：MPEG-4 形状编码器 二进制运动估计 超大规模集成电路 

分 类 号：TN762[电子电信—电路与系统]