基于全局伪路径的时钟特性分析新方法  

A new algorithm for timing characterization analysis based on global false path

作　　者：吴继娟[1] 刘晓晓 马光胜[1] 

机构地区：[1]哈尔滨工程大学计算机科学与技术学院,黑龙江哈尔滨150001

出　　处：《哈尔滨工程大学学报》2007年第1期71-74,共4页Journal of Harbin Engineering University

基　　金：国家自然科学基金资助项目(60273081)

摘　　要：为了得到确定精确的电路时延,将全局伪路径的观念引入到电路时钟特性分析中,提出了一种改进电路模块时钟周期准确性的方法.在不采取复杂空间搜索实现电路功能的情况下,该方法能给出正确的计算结果并且除去大多数的伪路径,最大限度地减少因伪路径而产生的性能错误.实验证明,新方法可以产生具有十分精确的路径延迟的时钟模型,对规模为几千个逻辑门的基准电路,可以在几十秒内得到电路的关键路径,而且得到的关键路径的时延比拓扑时延小很多,在相当大的程度上提高时钟模型的准确性.In order to obtain more accurate circuit delay,the notion of the global false path is applied to a previous timing analysis of circuits and a new timing characterization method was presented for improving the accuracy of timing models.This method is proved to generate timing models with very tight path delays that are guaranteed to give correct results and eliminate the vast majority of false paths without resorting to expensive search-based or symbolic techniques to account for functionality.Experimental results show that this method can be used on PC to fast detect critical paths of large-scale circuits and the circuit delay of critical paths may be much less than the topological analysis,thereby enhancing the accuracy of timing models.

关 键 词：时钟周期 电路延迟 关键路径 通路敏化 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]