Viterbi译码器的应用及其硬件设计与实现  

Hardware Implementation of Viterbi Decoder and Its Application

作　　者：安乐[1] 李实秋[1] 

机构地区：[1]重庆邮电大学,重庆400065

出　　处：《通信技术》2008年第5期26-28,共3页Communications Technology

摘　　要：维特比译码器是人们广泛采用的卷积码的译码器,在IS-95,GSM,3GPP中都有广泛的应用。文中首先简单说明Viterbi译码算法原理,接着分析Viterbi译码算法设计及伪代码实现,根据TD-SCDMA卷积码编码方案,设计了一种采用软判决方式的维特比译码器,并采用合理的归一化方式,保证了计算路径值的过程中不会发生溢出。仿真表明:改进的译码器具有良好的性能。Viterbi decoder is widely to implement convolutional decoding. It has been broadly applied in IS-95,GSM,3GPP. In this paper, the principle of Viterbi is briefed first, then the Viterbi decode design and Pseudo Code for the Viterbi Algorithm are analyzed. The paper described a Viterbi decoder based on convolutional coding scheme TD-SCDMA and with soft judgement. Simulations show that the modified decoder is robust and of better performance.

关 键 词：TD-SCDMA 信道编码 VITERBI VERILOG 

分 类 号：TN764[电子电信—电路与系统]