基于周期分割的复合式倍频器设计方法  

Hybrid method of frequency multiplier based on period dividing

作　　者：张多利[1] 程作仁[1] 杜高明[1] 贾靖华[1] 

机构地区：[1]合肥工业大学微电子设计研究所,合肥230009

出　　处：《仪器仪表学报》2006年第z2期1081-1083,共3页Chinese Journal of Scientific Instrument

基　　金：国家自然科学基金(60373076;60576034);教育部博士点基金(20050359003)

摘　　要：本文通过将基于周期分割的时钟倍频方法和ADPLL方法结合起来,将ADPLL中的鉴相和滤波方法引入到周期分割方法中,通过修改误差补偿算法,提高了周期分割的误差精度,实现了复合的时钟倍频电路设计方法,进行了基于硬件描述语言的电路设计,并完成仿真验证。理论分析和实验表明,该方法比原有方法有较大的改进。By combining the technique of period dividing with the method of ADPLL, a new method of frequency multiplying was proposed. The techniques of phase detection and digital filer in ADPLL were adopted into the period dividing method. Through modifying the algorithm of cycle insertion, the precision of period dividing was improved. With hardware description language verilog, the circuit was implemented and verified through simulator ModelSim. The Results of theorem analysis and experiments indicate that the hybrid method has better performance in latch time, scope and phase precision than the existing methods.

关 键 词：倍频电路 周期分割 ADPLL 

分 类 号：TH7-55[机械工程—仪器科学与技术]