二进制译码器综述  

Binary Decoders: A Survey

作　　者：高小鹏[1] 万寒[1] 

机构地区：[1]北京航空航天大学计算机学院,北京100083

出　　处：《系统仿真学报》2006年第z2期777-780,共4页Journal of System Simulation

基　　金：高等学校博士学科点专项科研基金(20030006026)

摘　　要：指令二进制码的译码过程是指令集模拟器、反汇编器以及调试器等软件的重要组成部分,译码效率直接影响到这类工具的性能。硬件译码中多个逻辑表达式可并发求值,而软件译码是串行过程,速率较低,成为ISS等软件工具性能提升的瓶颈。随着ISS由简单的解释型发展为编译型,二进制码译码器也随之朝着性能提升、可适用于多种体系结构、易于软件维护的方向发展。本文分析现有的典型指令模拟器的译码部分,并对其进行分类:由简单的逐条指令译码过程构成的循环,发展至直观的译码结果的缓存,再到利用编译器对译码过程的加速,以及针对ISS便于向多种体系结构移植而构建的译码器生成算法的研究。分析各种译码方式的优缺点,包括速率、可移植性及软件维护性等方面。The binary decoder is an important component of software tools such as instruction set simulators (ISSs), disassemblers and debuggers. The efficiency of the binary decoder directly affects the performance of these software tools, especially makes a strong impact on the ISS. The decoding based on hardware where multiple logic expressions can be evaluated concurrently; however, software decoding is a sequential flow. Therefore, the speed of binary decoding process becomes the performance bottleneck of the ISSs. As the ISS evolves from the simple interpretive simulator to compiled simulator, the decoder also developed towards the requirement about higher performance, retargetable and the easy-of-maintenance. The binary decoding process of existing ISSs was categorized, and the techniques were analyzed, such as word-for-word interpretive execution, the decoded results caching technique, the techniques based on compilation, and the algorithm of automatic synthesis of efficient binary decoders. The strengths and weaknesses of different approaches, including speed, flexibility, retargetbility and easy-of-maintenance are considered.

关 键 词：二进制码译码器 指令集模拟器 转换缓存 编译型模拟 决策树 可移植性 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]