64位整数加法器的设计与实现  

Design and Implement of 64-bit Integer Adder

作　　者：谭全林[1] 邢座程[1] 李少青[1] 陈延仓[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《微电子学与计算机》2009年第2期32-35,共4页Microelectronics & Computer

摘　　要：为了提高算术逻辑部件的性能,采用多米诺逻辑和偏斜逻辑门的电路结构,结合并行前缀加法器的优点,设计实现了一款64位高性能整数加法器.根据需要,设计了一种符号扩展电路,使之能够处理带符号操作数的加减法,符号扩展结果可以进行溢出判断.模拟结果表明:在0.13μmCMOS的工艺条件下,关键路径的延时为630ps功耗为21.6mW,达到了高速低功耗的设计目标.In order to improve the performance of Arithmetic Logical Unit(ALU),a 64-bit high-performance integer adder has been designed and implemented,combining the superiority of the parallel-prefix adder and using the structure of domino logic and asymmetry logic circuit.We devise a kind of sign-extended circuit for needed,which can processing signed operand and also can judge whether the result has overflowed.Simulation results show:the delay of critical path is 630ps with power of 21.6mW in 0.13μm CMOS process,i...

关 键 词：并行前缀加法器 多米诺逻辑 偏斜逻辑 功耗延时积 

分 类 号：TN791[电子电信—电路与系统]