数字PID控制器的硬件优化设计  

Optimization of digital PID controller on hardware

作　　者：蔡晓宁[1,2] 陈仲林[1] 董戈[1] 谢珊英[1,2] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《中国科学院研究生院学报》2010年第5期690-694,共5页Journal of the Graduate School of the Chinese Academy of Sciences

基　　金：国家高技术研究发展计划(863)项目(2007AA12Z123)资助

摘　　要：研究了PID控制器的数字电路实现方法.通过对数字PID算法进行流水线设计,提高了算法运行效率;通过对加法器和乘法器采用有符号二进制小数操作,减小了电路面积.该算法在ActelAFS600芯片上实现,仿真结果表明了该方案的可行性和有效性.PID control method is widely used in the feed-back circuit of switch mode power supply.Since the analog PID controller is sensitive to temperature and electromagnetic interference,we discuss hardware implementation of digital PID controller in the present paper.With pipeline operation the efficiency of the algorithm was improved,and with signed binary fraction operation the resource cost of the circuit was reduced.Finally,this digital PID algorithm was implemented on an Actel AFS600 FPGA chip,and simulation...

关 键 词：数字PID控制器 FPGA AFS600 流水线 SBF 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]