基于FPGA的RAID6硬件加速器的实现  

Design and Implementation of RAID6 Hardware Accelerator Based on FPGA

作　　者：董春[1] 施亮[1] 

机构地区：[1]上海交通大学自动化系CIMS实验室

出　　处：《微型电脑应用》2011年第1期5-6,15+4,共4页Microcomputer Applications

摘　　要：设计了基于FPGA的RAID6磁盘阵列的硬件加速器,将占用大量CPU周期的RAID6校验算法,用FPGA硬件实现并设计了软件与加速器的交互接口,将CPU从繁重的计算任务中解放出来,系统的处理速度和响应速度得到很大提升。In this paper, a hardware accelerator based on FPGA for RAID6 parity generation is introduced,software parity calculation is replaced by hardware means and interface is designed to enable intercommunication between RAID firmware and the accelerator. All this releases the CPU from intensive calculations, processing and responding speed of the system are greatly improved.

关 键 词：RAID6FPGA 伽罗瓦域 里德-所罗门编码 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]