一种基于FPGA的ISA航空总线设计方法  

Implementation of ISA Aviation Bus Interface on FPGA System

作　　者：安磊[1] 梁尚军[1] 邴洋海[1] 

机构地区：[1]中国人民解放军驻沈阳飞机工业集团有限公司军事代表室,辽宁沈阳110034

出　　处：《飞机设计》2012年第4期45-49,共5页Aircraft Design

摘　　要：Nios Ⅱ处理器是Altera公司推出的基于SOPC系统的嵌入式软核处理器。在Quartus Ⅱ软件的SOPC Builder工具中,用户可以利用Nios Ⅱ处理器、标准配套外围设备以及用户自定义的逻辑接口IP核来创建适用的Nios Ⅱ嵌入式系统,再将设计下载到Altera公司的FPGA中进行实现。本文在Quartus Ⅱ软件中使用Verilog硬件描述语言创建了基于Avalon总线的ISA总线接口逻辑,并在SOPC Builder中实现对此元件的封装,使之成为可供Nios Ⅱ系统使用IP核。The Nios Ⅱ processor is a configurable soft-core processor provided by Altera Corporation for its SOPC(System On Programmable Chip).In SOPC Builder software,the user may customize a Nios Ⅱ processor system by combining Nios Ⅱ soft-core processor,standard peripherals and even user-defined IP cores,to meet special performance requirements of an embedded system.This paper described an ISA-to-Avalon bus interface logic with Verilog HDL in Quartus Ⅱ,and packaged which into an SOPC Builder component in the use of SOPC Builder component editor wizard.Thus an user-defined IP core is added into the Nios Ⅱ processor system.Then a Nios Ⅱ embedded system may directly communicate with ISA bus peripherals with this IP core.

关 键 词：NIOS Ⅱ处理器 FPGA 自定义IP核 VERILOG硬件描述语言 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]