辐射加固SOI工艺FPGA的设计与验证  

Design and verification of radiation-hardened by SOI-based FPGA

作　　者：吴利华[1] 韩小炜[1] 赵岩[1] 于芳[1] 刘忠立[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《信息与电子工程》2012年第5期627-632,共6页information and electronic engineering

摘　　要：进行了一款辐射加固SRAM基VS1000 FPGA的设计与验证。该芯片包含196个逻辑模块、56个IO模块、若干布线通道模块及编程电路模块等。每个逻辑模块由2个基于多模式4输入查找表的逻辑单元组成,相对传统的4输入查找表,其逻辑密度可以提高12%;采用编程点直接寻址的编程电路,为FPGA提供了灵活的部分配置功能;通过对编程点的完全体接触提高了全芯片的抗辐射能力。VS1000 FPGA基于中电集团第58所0.5μm部分耗尽SOI工艺进行辐射加固设计并流片,样片的辐照试验表明,其抗总剂量水平达到1.0×105rad(Si),瞬态剂量率水平超过1.5×1011rad(Si)/s,抗中子注量水平超过1.0×1014n/cm2。A radiation-hardened SOI-SRAM-based Field Programmable Gate Array(FPGA) VS1000 is designed and verified.The VS1000 FPGA contains 192 reconfigurable Logic Blocks(LB),56 reconfigurable Input/Output logic Blocks(IOBs),some routing channel blocks(CHBs) and programming blocks(PGMs).An LB consists of 2 Logic Cells(LCs) based on multi-mode 4-input Look-Up-Table(LUT),which increases logic density by 12% compared to a traditional 4-input LUT.PGM adopts direct-access programming point scheme and provides a more flexible partial configuration.Programming Point(PP) is specially designed using full body-tied techniques to improve radiation-hardened performance of chip.The VS1000 FPGA is designed and fabricated with a 0.5 μm Partial-Depletion Silicon-On-Insulator(PDSOI) logic process at the 58th institute of CETC.The radiation test results indicate that VS1000 FPGA bears total dose tolerance of 1×105 rad(Si),dose rate survivability of 1.5×1011 rad(Si)/s and neutron fluence immunity of 1×1014 n/cm2.

关 键 词：辐射加固 现场可编程逻辑门阵列 逻辑单元 部分配置 部分耗尽SOI 

分 类 号：TN791[电子电信—电路与系统]