降低STI效应的D触发器标准单元设计  

Design on D Flipflop Standard Cell with Decrease of STI Effect

作　　者：王鑫华[1] 李斌[2] 邹振杰[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《计算机与网络》2013年第24期61-64,共4页Computer & Network

摘　　要：在深亚微米集成电路中,浅槽隔离(STI)效应会影响电路的性能。将NMOS管的源极有源区长度增大后,STI效应的影响会减小,D触发器的功耗延迟积也会随之减小。TCAD器件仿真同时显示,这种减小不是无限度的。这是因为STI隔离存在非理性因素,随着STI宽度减小,器件之间的漏电流也会增大。对减小STI效应的D触发器电路进行了仿真,增加NMOS有源区长度0.1?m时,其功耗延迟积比原来降低了3%。利用建库工具将D触发器的时序和功耗等信息抽取成库文件,可供数字电路综合时调用,将其做成标准单元后,加入到SMIC65nmCMOS库中可以应用于低功耗的半定制数字集成电路设计。In the deep submicron integrated circuit,the shallow trench isolation(STI) effect will affect the circuit performance.After increasing the length of N MO S source active region,the influence of STI effect will decrease,and the power delay product(PDP) of D flipflop will also decline.The TCAD device simulation shows that the decrease is not unlimited.This is because the STI isolation has irrational factors,the leakage current between devices will increase with the decrease of STI width.The simulation of circuit of D flip- flop with decrease of STI effect is carried out,the PDP is decreased by 3% when the length of N MO S active region is increased by 0.1?m.by using the building tool,the time sequence and power dissipation of D flipflop is extracted as the library file,which is used for digital circuit synthesis.The flipflop standard cell with low PDP is introduced into SMIC 65nm CMO S libraries,which can be applied to the low- dissipation semi custom digital integrated circuit design.

关 键 词：浅槽隔离 功耗延迟积 标准单元设计 迁移率 版图设计 

分 类 号：TN783[电子电信—电路与系统]