一种串行结构的2,1,7卷积码维特比译码器的FPGA实现  

A Serial-structured Viterbi Decoder Design for(2,1,7)Convolution Code on FPGA

作　　者：黄华柱[1] 刘荣科[1] 王闰昕[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100083

出　　处：《遥测遥控》2009年第3期54-58,共5页Journal of Telemetry,Tracking and Command

摘　　要：卷积码在通信系统中得到了极为广泛的应用,其中约束长度K=7,码率为1/2的卷积码己经成为商业卫星通信系统中的标准编码方法。但是,目前的维特比译码器消耗的资源过多,制约了它的应用,因此迫切需要实现资源消耗少的维特比译码器。文中提出一种(2,1,7)卷积码维特比译码器的实现方案,该译码器采用串行结构的加/比/选模块,将加/比/选模块、最小路径判决和度量存储作为一个整体来设计,并采用两个存储器存储路径度量值,进行乒乓操作。这样设计的好处是一方面提高了速度,另一方面节省了资源。该译码器还对传统的回溯模块进行改良,与已有的串行结构的译码器相比,在速度相同的前提下,消耗的资源节省了80%。The convolution code has broad application in communication systems.The convolution code with constraint length K=7,code rate=1/2 has become the standard encoding method in the commercial satellite communication system.But the Viterbi decoder consumes so much resource that it limits the convolution code’s application.So it is necessary to achieve the Viterbi decoder that consumes less resourse.This paper presents a design of a(2,1,7)convolution code’s Viterbi decoder.The decoder uses the ADD/COMPARE/SELECT(ACS)module which is serial-structured and the operation of 'ping pang' of two memories of paths to save resource.The ACS module and the smallest path metric are designed as a whole so as to improve the speed and save the resource.The decoder changes the module of TB to make it better.In case of the same speed,this decoder saves eighty percent resource compared with the decoder mentioned in reference 2.

关 键 词：卷积码 维特比译码器 FPGA 串行 

分 类 号：TN764[电子电信—电路与系统]