满足高密度组装的SMT三维封装堆叠技术  

3D Stacking Packaging in SMT for High Density Packaging

作　　者：胡志勇[1] 

机构地区：[1]华东计算技术研究所,上海201233

出　　处：《印制电路信息》2009年第10期58-61,69,共5页Printed Circuit Information

摘　　要：随着人们对手持式电子设备不断提出的微型化、多功能化和集成化的需求,转化为采用三维(3D)方式装配印制电路板(PCB)强大推动力。实现三维装配的成功道路之一是通过在芯片规模封装(CSP)采用晶芯堆叠的方法,实现三维装配的另外一条成功之路是通过封装器件的堆叠来实现。文章中将封装堆叠作为SMT工艺流程中的一个组成部分进行了介绍。The need for continued miniaturization,functional densification and integration in handheld electronics products provides the strong incentive for printed circuit board(PCB)assembly in three-dimensions(3D). One way to accomplish 3D assembly is through the use of die stacking in chip scale packages(CSP).The other way to accomplish 3D assembly is through the use of package stacking.In this paper,package stacking as part of the SMT process is described.

关 键 词：三维堆叠 封装 表面贴装技术 高密度 电子组装 

分 类 号：TN405[电子电信—微电子学与固体电子学]