ASIC Design of M13  

作　　者：葛宁 

机构地区：[1]Communication Division,Department of Electronic Engineering,Tsinghua University,Beijing 100084,P.R.China

出　　处：《High Technology Letters》1996年第2期21-24,共4页高技术通讯（英文版）

基　　金：the High Technology Research and Development Programme of China.

摘　　要：The MX3101 E3/E1 Multiplexer/Demultiplexer(M13)device with digital cross-connec-tors is the first industrial semiconductor chip which can provide the whole circuitry neededfor a complete plesiochronous E3/E1 multiplexer/demultiplexer on a single CMOS VLSI de-vice.By a novel all-digital phase-locked loop(PLL)and a timing regeneration circuit,thewhole system is integrated on a LSILogic’s LCA405K gate array ASIC with 50K gates and144 pins.The MX3101 E3/E1 Multiplexer/Demultiplexer(M13)device with digital cross-connec- tors is the first industrial semiconductor chip which can provide the whole circuitry needed for a complete plesiochronous E3/E1 multiplexer/demultiplexer on a single CMOS VLSI de- vice.By a novel all-digital phase-locked loop(PLL)and a timing regeneration circuit,the whole system is integrated on a LSILogic's LCA405K gate array ASIC with 50K gates and 144 pins.

关 键 词：M13 ASIC ALL-DIGITAL 

分 类 号：TN492[电子电信—微电子学与固体电子学]