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Current status and development of CMOS SiPM for scintillator-based radiation detectors toward all-digital sensors[Invited]被引量：1: 《Chinese Optics Letters》2024年第2期17-27,共11页Nicola D'Ascenzo 胡文韬劳慧华越轩张博房磊奚道明郑睿邱奥 Emanuele Antonecchia 凌怡清刘雨晴李琰俞航肖鹏谢庆国; supported by the National Natural Science Foundation of China(Nos.62250002,62027808,and 62027801);the Sino-German Mobility Programme(No.M-0387)。; Modern scintillator-based radiation detectors require silicon photomultipliers(Si PMs)with photon detection efficiency higher than 40%at 420 nm,possibly extended to the vacuum ultraviolet(VUV)region,single-photon time...; 关键词：silicon photomultiplier complementary metal-oxide semiconductor digital SiPM

A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy被引量：1: 《Journal of Semiconductors》2020年第12期41-49,共9页Xian Zhang Xiaodong Cao Xuelian Zhang; In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration ...; 关键词：foreground all-digital calibration RS strategy RS-based dither auto-zero comparator SAR ADC

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits被引量：1: 《Science China(Information Sciences)》2019年第6期106-121,共16页Jincheng YANG Zhao ZHANG Nan QI Liyuan LIU Jian LIU Nanjian WU; supported by National Nature Science Foundation of China (Grant Nos. 61331003, 61474108, 61234003);National Key Technology Research and Development Program of the Ministry of Science and Technology of China (Grant No. 2016ZX03001002); This paper proposes a synthesized injection-locked bang-bang phased-locked loop(SILBBPLL)with high digital controlled oscillator(DCO) frequency resolution. The SILBBPLL is expressed with hardware description language ...; 关键词：SYNTHESIZED ALL-DIGITAL phased-locked loops(ADPLL) bang-bang phased-locked loop(BBPLL) automatically placed & routed(APR) output feedback DAC(OFDAC) INJECTION-LOCKED

A high-accuracy DCO with hybrid architecture: 《Journal of Semiconductors》2017年第7期111-116,共6页Yapeng Sun Huidong Zhao Shushan Qiao Yong Hei Fuhai Zhang; supported by the National Natural Science Foundation of China(Nos.61306025,61474135); In this paper, a novel hybrid digital-controlled oscillator（DCO） is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consi...; 关键词：high accuracy DCO all-digital PVT variations

All-Digital Self-Interference Cancellation in Zero-IF Full-Duplex Transceivers被引量：4: 《China Communications》2016年第11期27-34,共8页Lu Tian Shuai Wang Zhiheng Cheng Xiangyuan Bu; supported in part by the National Natural Science Foundation of China(No.61601027); In this paper,a general scheme in digital self-interference cancellation at baseband for zero-IF full-duplex transceivers is presented. We model the self-interference signals specifically with only the nonlinear disto...; 关键词：communication systems full-duplex transceivers self-interference cancellation IQ imbalance de-correlated normalized least mean square algorithm

A low-power,area-efficient all-digital delay-locked loop for DDR3 SDRAM controller被引量：1: 《Science China(Information Sciences)》2014年第12期172-179,共8页CHEN HongMing MA Song WANG Liu ZHANG Hao PAN KenYi CHENG YuHua; supported by National 02 Key Special Program(Grant No.2009ZX02305-005);National Hightech R&D Program of China(863 Program)(Grant No.2013AA014102);National No.2 Special Key ProjectProgram(Grant No.2012ZX02503005); A new low-power, area efficiency all-digital delay-locked loop （ADDLL） circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz （DDR3- 667/800/1066/1...; 关键词：all-digital delay-locked loop double-data-rate digitally controlled delay line shunt capacitor thermometer code

An all-digital synthesizable baseband for a delay-based LINC transmitter with reconfigurable resolution: 《Journal of Semiconductors》2014年第11期98-106,共9页韩越乔树山黑勇; The linear amplification with nonlinear component transmitter is a promising solution to high efficiency and high linearity amplification for non-constant envelope signals. An all-digital synthesizable baseband for a ...; 关键词：low power linear amplification with nonlinear component （LINC） ALL-DIGITAL synthesizable

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology: 《Journal of Semiconductors》2013年第3期81-85,共5页江晨黄煜梅洪志良; supported by the Important National Science and Technology Specific Projects of China(No.2009ZX01031-003-002); A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input sta...; 关键词：time-to-digital converter gated ring oscillator effective resolution all-digital phase locked loop

A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA: 《Journal of Semiconductors》2011年第10期139-146,共8页陈柱佳杨海钢刘飞王瑜; Project supported by the Major National Scientific Research Plan of China(No.2011 CB933202);the National High Technology Research and Development Program of China(No.2008AA010701); A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） c...; 关键词：all digital DLL DDR SDRAM controller time-to-digital converter duty cycle corrector DCDL FPGA

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS: 《Journal of Electronics(China)》2008年第5期673-678,共6页Deng Xiaoying Yang Jun Shi Longxing Chen Xin; A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...; 关键词：All-Digital Phase Locked Loop （ADPLL） Digital Controlled Oscillator （DCO） Impulse Sensitivity Function （ISF） Thermal noise JITTER

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