SerDes技术中高速串行信号采样原理与实现  

The Mechanism and Implementation of Sampling Rapid Serial Signal in SerDes Technique

作　　者：胡封林[1] 刘宗林[1] 陈海燕[1] 陈吉华[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《微电子学与计算机》2015年第5期25-30,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61070036)

摘　　要：在接收端对高速信号的采样处理是SerDes技术中的核心技术之一.基于采样原理,提出并构建数字采样模型,并给出了解决此类问题的一般方法.作为一个应用实例,采用8相,且每相邻两相相差45度的采样时钟,对12.5Gb/s的8B/10B编码的高速串行数据进行采样处理.硬件上,高速串行信号采样电路采用了5级锁存栈,其中两级钟控敏感放大器(CSA)级联,一级CTOL数据双端转单端锁存器,一级CMOS同步D型锁存器进行相位调整,一级CMOS同步D型锁存器.5级锁存栈较好地实现了对高速串行信号的采样,经模拟验证,电路正确地采样了输入信号,其结果无漏无重,完全正确.The sampling on rapid signal at the receiver is one of the key technolog.On the basis of sampling theory,a digital sampling model is set up and a general method of solving those questions is put forward.As an applicational instance,8-phase sampling clock is proposed.The clock,with 45degrees' discrepancy between adjacent phases,samples 12.5 Gb/s rapid serial data coded in 8B/10 B.In the sampling circuit of hardware,5-level flip-latch is employed.There are two level cascaded with CSA,one with CTOL flip-latch for two-line to one-line,one with CMOS D-type synchronization flip-latch for phase tune and one with CMOS D-type synchronization flip-latch The sampling has been implemented on 5levels in logical design.The consequence is simulated and verified to be accurate.

关 键 词：SerDes技术 采样 CDR CMOS 高速串行信号 

分 类 号：TN911.7[电子电信—通信与信息系统]