标志预访问和组选择历史相结合的低功耗指令cache  

Pre-Visiting Tag and Keeping Way History to Reduce Power in Instruction Cache

作　　者：张宇弘[1] 王界兵 严晓浪[3] 汪乐宇[1] 

机构地区：[1]浙江大学数字技术及仪器研究所,浙江杭州310027 [2]中天微系统有限公司,浙江杭州310027 [3]浙江大学VLSI研究所,浙江杭州310027

出　　处：《电子学报》2004年第8期1286-1289,共4页Acta Electronica Sinica

基　　金：国家 8 63重大科技攻关项目 32位C CORE嵌入式CPU开发 (No .2 0 0 2AA1Z1 0 50 )

摘　　要：指令cache是处理器的主要耗能部件之一 .研究发现 ,在指令顺序执行的情况下 ,访问同一cache行只需要访问一次标志存储器 ,因此标志存储器存在大量空闲周期 .本方法利用标志存储器的空闲周期来预先访问地址连续的下一个cache行的标志 ,从而预先获得cache行命中和组选择信息 ,这样当真正取下一行的指令时 ,根据获得的该cache行的标志信息就无需访问没有被选中的数据存储器 .预先访问标志存储器的另一个优点是可以加入组预测算法来减少对标志存储器的访问 .为了减少短距离跳转时对cache的访问 ,环形历史缓冲区 (CHB)保存了部分组选择结果来获得跳转目标地址的cache行信息 .该方法没有性能损失 ,而且具有硬件实现简单 ,硬件代价小等优点 .该方法已被应用于 2 5 0MHz的RISC处理器中 .Instruction cache consumes a large portion of power in processor. By using this method the number of accesses to both tag and data array of set-associative instruction cache can be significantly reduced. The method takes advantage of the fact that tag can be accessed once per line during sequential execution. And in the idle cycles of the tag memory, the next cache line can be pre-visited so that the cache-hit and way-select information can be obtained ahead of time. This information can be used to chip-deselect the missed data array later. Also way prediction mechanism can be utilized in tag pre-visiting scheme to further reduce the number of accesses to the tag array without performance penalty. A way-select circular history buffer (CHB) is maintained to record way-select information of a cache line. Short branches within the address range of the CHB will not require accessing to the tag array and missed data array. This method has been implemented in a 250 MHz high-performance low-power RISC processor.

关 键 词：CACHE 低功耗 CPU 微体系结构 

分 类 号：TN47[电子电信—微电子学与固体电子学]