一种面向系统芯片的FPGA协同验证方法  

A Concurrent Strategy of FPGA’s Verification for System-on-Chip

作　　者：杨焱[1] 侯朝焕[2] 

机构地区：[1]中国科学院研究生院,北京100080 [2]中国科学院声学所,北京100080

出　　处：《微电子学》2004年第4期469-472,共4页Microelectronics

基　　金：国家重点基础研究发展规划(973)资助项目(G1999032904)

摘　　要：　利用多片FPGA对SOC系统进行功能验证时,原始的系统分割策略常常导致欠优化的结果,有时甚至会付出重新设计的高昂代价。文章在静态时序分析的基础上,提出了一种利用关键路径时延信息提高FPGA分割效率的方法。分割结果表明,该方法能显著改善功能验证效率,明显提高逻辑控制块和I/O的利用率。文中同时讨论了该协同验证策略在处理信号完整性与RTL设计脱节时所具有的优势。The original partition strategy often causes less optimization result when used to verify the functions of SOC with multi-FPGA’s.Even the cost of design is so high that designers have to redesign the system.In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.The result of partition demonstrates that the method could significantly improve the efficiency of functional verification and the utilization ratio of CLB’s and I/O.Finally, the advantage of co-verification dealing with the interrelation between signal integrity and RTL design is discussed.

关 键 词：系统芯片 FPGA 协同验证 路径时延 静态时序分析 

分 类 号：TN492[电子电信—微电子学与固体电子学]