用EMODL实现的高速低功耗流水线乘法器  

High Speed Low Power Pipelined Multiplier Using EMODL

作　　者：王颀[1] 邵丙铣[1] 

机构地区：[1]复旦大学国家电子材料与元器件微分析中心,上海200433

出　　处：《固体电子学研究与进展》2004年第3期363-368,共6页Research & Progress of SSE

摘　　要：实现快速、低功耗以及节省面积的乘法器对高性能微处理器 (例如 DSP和 RISC)而言是至关重要的。文中详尽论述了新型的增强型多输出多米诺逻辑 ( EMODL)及其 n-MOS赋值树的尺寸优化方法 ,并用它实现了高速低功耗 2 0× 2 0 bit流水线乘法器。最后 ,通过 HSPICE仿真 ,确认了该乘法器结构的优越性 :流水线等待时间小 ( 2倍于系统时钟 )、运算速度高 ( 10 0 MOPS)以及低功耗 ( 2 3 .94m W)It is crucial to implement a multiplier of high speed,low power dissipation and low area consumption in high performace microprocessors such as DSP & RISC.A novel Enhanced Multiple-Output Domino Logic(EMODL)^() and the sizing optimization of its n-MOS (evaluation) tree are covered in detail in this paper.It is utilized to implement a fast 20×20 bit pipelined multiplier with low power consumption.Finally,through HSPICE simulation,we verified that the multiplier structure excels in short pipeline latency time(2 times the system clock period)and high operation speed (100 MOPS)with low power dissipation(23.94 mW).

关 键 词：乘法器 流水线电路结构 多米诺逻辑 动态逻辑 超前进位加法器 

分 类 号：TN432[电子电信—微电子学与固体电子学]