基于多相滤波高效结构的宽带DDC及其FPGA实现  

Wideband DDC Based on Polyphase Structrue and Its FPGA Implementation

作　　者：吴伟[1] 唐斌[1] 张鹏[1] 

机构地区：[1]电子科技大学电子工程学院,成都610054

出　　处：《数据采集与处理》2004年第2期210-214,共5页Journal of Data Acquisition and Processing

基　　金：军事电子预研资助项目

摘　　要：针对雷达数字接收系统中存在前端 A/ D输出的高速数据流与后端 DSP的低吞吐率之间难以匹配的问题 ,从传统数字下变频的结构出发 ,推导出宽带数字下变频的多相滤波高效结构 ,信道之间重叠 5 0 % ,采用并行结构实现高速、高效滤波 ,只计算被抽取点数据 ,极大地提高了运算效率及算法的工程可实现性。计算机仿真及用大规模现场可编程门阵列的硬件实现验证了此方法的正确性和有效性。The great gap between the high-speed data flow from A/D converter and low-speed of DSP is a bottleneck limiting the study of radar digital receiving system. The polyphase filter structure of the wideband digital down conversion (DDC) is deduced from the structure of the conventional digital downconverter. Its channels are 50% overlapped. It can realize the high speed and efficient filtering by using the parallel structure and only calculate the decimated data,thus improving the operational efficiency and realizability. The correctness and the validity are proved by the computer simulations and the field programming gate array (FPGA) implementation.

关 键 词：雷达 数字接收系统 宽带DDC FPGA 可编程门阵列 数据流 

分 类 号：TN957.5[电子电信—信号与信息处理]