SrTiO_3陶瓷晶界层电容器材料的晶界研究——Ⅱ.晶界模型与材料电性能  

STUDY ON GRAIN BOUNDARY OF SrTiO_3 GBBL CAPACITORS——Ⅰ.GRAIN BOUNDARY MODEL AND ELECTRIC PROPERTIES

作　　者：徐保民[1] 宋祥云[1] 王鸿[2] 殷之文[1] 温树林[1] 

机构地区：[1]中国科学院上海硅酸盐研究所,上海200050 [2]上海科学技术大学材料科学系

出　　处：《硅酸盐学报》1993年第6期519-527,共9页Journal of The Chinese Ceramic Society

摘　　要：根据低温一次烧结SrTiO_3陶瓷晶界层电容器两晶粒间晶界相结构的复杂性和不同晶界的势垒特性,建立了具有复合晶界特征的晶界等效电路模型,据此解释了材料的I-V非线性特性和介电-电压特性。认为低施主掺杂的材料,击穿区的I-V非线性特性主要是由通过“洁净”晶界和窄晶界的隧道电流引起的,从而与温度无关;而高施主掺杂的材料,击穿区的I-V非线性特性既包括通过“洁净”晶界和窄晶界的隧道电流,亦包括通过宽晶界的雪崩击穿电流,从而与温度有关。在低的直流偏压下,材料的电容量随偏压变化很小,但由通过“洁净”晶界和部分窄品界而贯穿样品的热激发漏导电流的存在,使材料的介电损耗明显增加。According to the complexity of intergranular phase and the barrier characteristics of various grain boundaries, a new equivalent circuit model with composite grain boundary characteristics is proposed, showing successfully the Ⅰ-Ⅴ nonlinear characteristics and dielectric property-voltage relation. For the low donor doping materials, the Ⅰ-Ⅴ nonlinear characteristics in breakdown region is caused by the tunnel current through the 'clean' grain boundary and the narrow grain boundary, and is independent on temperature. However, for the high donor doping materials, the Ⅰ-Ⅴ nonlinear characteristics is caused by the avalanche current through. the wide grain boundary, and by the tunnel current through the 'clean' grain boundary and the narrow grain boundary, and is dependent on temperature. The voltage dependence of capacitance is small under low DC bias, but the dielectric loss obviously increases with DC bias, which is caused by the thermally activated current crossing samples through the 'clean' grain boundary and the narrow grain boundary.

关 键 词：钛酸锶陶瓷 晶界层电容器 晶界模型 

分 类 号：TM534.1[电气工程—电器]