IDCT IP核的VLSI结构  

Architecture of VLSI for IDCT IP Core

作　　者：饶海潮[1] 郭立[1] 黄征[1] 

机构地区：[1]中国科技大学集成电路与系统实验室,安徽合肥230026

出　　处：《微电子学与计算机》2004年第8期132-134,共3页Microelectronics & Computer

摘　　要：介绍了一种新型的IDCTIP核的VLSI结构,这种并行结构结合分布式算法和基于存储器的查找表,系统自顶向下分解为模块,设计出一个不需要乘法器的高性能IP核,可以实时处理MPEG2MP@ML。This paper introduces a new VLSI architecture for IDCT IP core. The pa rallel architecture combines distributed algorithm and look-up table based memor y. The system is divided into modules from the top to down.. A high performance IP core is designed without multiplier and can process MPEG2 MP@ML in real time .

关 键 词：离散余弦反变换 IP核 乘累加单元 

分 类 号：TN4[电子电信—微电子学与固体电子学]