基于CPLD的锁相位同步信号提取技术  

Getting Technology of Bit Alignment Signal of Phase-locked Loop Based on CPLD

作　　者：狄京[1] 张申[1] 庄乾启[1] 冯小龙[1] 张红梅[1] 

机构地区：[1]中国矿业大学信电学院,江苏徐州221008

出　　处：《工矿自动化》2004年第5期12-14,共3页Journal Of Mine Automation

摘　　要：锁相位同步提取技术是通信系统中一个重要的实际问题。现介绍一种用CPLD复杂可编程逻辑器件为控制核心 ,采用AHDL语言编程实现数字锁相位同步信号提取的方法。使整体设计、功能实现更加稳定、可靠。The technology of getting the bit alignment signal of phase-locked loop is a very important practical problem in communications system. This paper introduced a system to pick up the bit alignment signal of digital phase-locked loop which is programmed in AHDL language and its CPU is CPLD (Complicated Programmable Logic Device). Using this technology, the system will be more stable and credible in its configuration design and function realization.

关 键 词：通信系统 数字锁相环 位同步信号 CPLD AHDL 

分 类 号：TN911.8[电子电信—通信与信息系统]