高性能微处理器微体系结构级功耗模型及分析  

Microarchitecture-Level Power Modelling and Analyzing for High-Performance Microprocessors

作　　者：王永文[1] 张民选[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机学报》2004年第10期1320-1327,共8页Chinese Journal of Computers

基　　金：国家自然科学基金 (60 2 73 0 69;90 2 0 70 11)资助

摘　　要：基于Itanium 2微处理器体系结构提出单时钟和多时钟域两种基准模型 ;对处理器的电路级特性进行微体系结构级抽象 ,建立了参数化的峰值功耗估算模型 ;提出事件调度算法 ,实现了多时钟域处理器系统的行为级模拟 ;以IMPACT工具集作为模拟引擎实现了处理器的动态功耗模拟模型 .与其它同类模型Wattch相比 ,该模型能够支持多时钟系统的模拟 ,峰值功耗估算精度高了约 3% ,而模拟速度提高了 4 2 % .通过实验说明了多时钟域的功耗特性 ,在一种多电压和频率环境下 ,多时钟域处理器的功耗和能量分别降低了 2 1%和 38% .该模型可以很好地应用到体系结构级低功耗研究设计 .Power dissipation is becoming a serious challenge to microprocessor design, which requires to consider power and performance trade-offs during architecture design phase. Two baseline architecture models with single clock and multi-clock domains respectively are presented based on the Itanium 2 microprocessor architecture. The circuit characteristics are abstracted at microarchitecture level and a microarchitectural peak power estimation model is implemented. An event-scheduling algorithm is presented to support the simulation of the multi-clock-domain systems. The dynamic power simulation model is implemented based on the IMPACT simulation engine. Compared with similar model Wattch, the peak power estimation accuracy is improved by 3% and the simulation speed is improved by 42%. Experiment is also made to demonstrate the power efficiency of multi-clock-domain system. In one scenario of multi-clock and multi-voltage control, the power and energy are reduced by 21% and 38% respectively with acceptable performance loss. This power model is suitable for architecture-level low power design.

关 键 词：微处理器 微体系结构 功耗模型 模拟器 低功耗设计 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]