Strained Si Channel Heterojunction pMOSFET Using 400℃ LT-Si Technology  

应用400℃低温Si技术制备应变Si沟道pMOSFET(英文)

作　　者：梅丁蕾[1] 杨谟华[1] 李竞春[1] 于奇[1] 张静[2] 徐婉静[2] 谭开洲[2] 

机构地区：[1]电子科技大学微电子与固体电子学院,成都610054 [2]模拟集成电路国家重点实验室,重庆400060

出　　处：《Journal of Semiconductors》2004年第10期1221-1226,共6页半导体学报（英文版）

基　　金：模拟集成电路国家重点实验室基金资助项目 (合同号 :2 0 0 0 JS0 9.3 .1.DZ0 2 )~~

摘　　要：A novel MBE-grown method using low-temperature (L T) Si technology is introduced into the fabrication of strained Si channel heter ojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At th e same time,the threading dislocations (TDs) are hold back from propagating to t he surface.As a result,the thickness of relaxed Si 1-xGe x epitax y layer on bulk silicon is reduced from several micrometers using UHVCVD to less than 400nm(x=0.2),which will improve the heat dissipation of devices.AFM t ests of strained Si surface show RMS is less than 1.02nm.The DC characters meas ured by HP 4155B indicate that hole mobility μ p has 25% of maximum enhanc ement compared to that of bulk Si pMOSFET processed similarly.在利用分子束外延方法制备 Si Ge p MOSFET中引入了低温 Si技术 .通过在 Si缓冲层和 Si Ge层之间加入低温 Si层 ,提高了 Si Ge层的弛豫度 .当 Ge主分为 2 0 %时 ,利用低温 Si技术生长的弛豫 Si1 - x Gex 层的厚度由UHVCVD制备所需的数微米降至 4 0 0 nm以内 ,AFM测试表明其表面均方粗糙度 (RMS)小于 1.0 2 nm.器件测试表明 ,与相同制备过程的体硅 p MOSFET相比 ,空穴迁移率最大提高了 2 5 % .

关 键 词：SIGE low-temperature Si strain relaxation threadi ng dislocation 

分 类 号：TN386[电子电信—物理电子学]