安全逻辑器件与CMOS B/T逻辑电路及其噪声容限  

Safe Logic Elements CMOS B/T Logical Circuits and Their Noise Margins

作　　者：江建慧[1] 胡谋[1] 

机构地区：[1]上海铁道学院可靠计算系统研究室,200333

出　　处：《计算机研究与发展》1993年第5期55-61,7,共8页Journal of Computer Research and Development

摘　　要：本文从容错计算技术的使用效果出发,将其分为故障诊断、资源冗余和故障安全三类技术。在分析传统故障安全技术的基础上,建立了一个统一的安全逻辑系统概念模型,并以此对该种系统进行了分类。作为一类扩展故障安全逻辑器件,文章重点介绍了三中取二值CMOS 逻辑电路,并参照CMOS 二值集成电路参量体系,结合实际测量结果提出了CMOS 三中取二值逻辑器件噪声容限的定义及其解法,从而为进一步完善该类新型器件的参量体系奠定了基础,同时还有利于其推广应用。In this paper,the fault tolerant computing techniques are classified into three classes, that is,fault diagnosis technique,resourses redundancy technique and fail-safe technique.Based on the analysis of traditional fail-safe and self-checking techniques,a unified conceptual model of safe logic systems is developed,and some classes of safe elemeats are diseussed.As a class of extended fail-safe logical element,CMOS 2-of-3 valued logical circuits are analyzed,The definition and gragh method of noise margin of CMOS 2-of-3 valued logical elcments are proposed.

关 键 词：容错 故障安全 噪声容限 逻辑电路 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]