一种Montgomery模乘的硬件算法及其实现  

A Hardware Algorithm for Montgomery's Modular Multiplication and Its Implementation

作　　者：方颖立[1] 高志强[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学》2002年第4期276-278,282,共4页Microelectronics

摘　　要：采用大数的高基表示方法对原 Montgomery算法进行了改进 ,提出了一种高效的面向硬件的计算 Montgomery积的算法 ,按照该算法实现的硬件具有较低的复杂度和较高的处理速度 ,并且利用 CSMC的 0 .6 μm CMOS标准单元库实现了 5 1 2位的 Montgomery模乘器。该模乘器约含480 0 0等效门 ,面积约为 3 mm× 3 mm,最高工作时钟频率可达 40 MHz,完成 5 1 2位 Montgomery模乘需要 3 4A high radix technique is employed to improve the original Montgomery's algorithm,and an efficient hardware oriented algorithm is proposed to calculate Montgomery Product, which has a reduced hardware complexity and increased processing speed The algorithm has been implemented in a 512 bit Montgomery modular multiplier using CSMC 0 6 μm CMOS standard cell library The device contains about 48k gates and occupies an area of 3 mm × 3 mm Operating at a maximum clock frequency up to 40 MHz, it takes 341 clock cycles for the modular multiplier to accomplish a 512 bit Montgomery modular multiplication

关 键 词：模乘器 MONTGOMERY算法 专用集成电路 

分 类 号：TN431.20[电子电信—微电子学与固体电子学] TN4