一种并行结构的二维正/逆整数变换处理器  

A 2D Forward and Inverse Integer Transform Processor Based on Highly-Parallel Architecture

作　　者：刘凌志[1] 戎蒙恬[1] 姜黎[1] 

机构地区：[1]上海交通大学电子工程系,上海200030

出　　处：《上海交通大学学报》2004年第12期2048-2051,共4页Journal of Shanghai Jiaotong University

基　　金：国家高技术研究发展计划(863)项目(2003AA1Z1070)

摘　　要：提出了一种适用于MPEG-4AVC/H.264压缩编码标准的二维正/逆整数变换处理器.利用正/逆变换的相似性和对称性实现高度并行结构,采用一维正/逆变换单元复用的方式来实现二维正/逆变换,用并行寄存器组实现矩阵转置运算.在0.35μm工艺下,其逻辑门数仅为3524,处理速度大于120MHz.A 2D forward and inverse integer transform processor for MPEG-4 AVC/(H.264) visual profile was presented. The comparability between the forward and inverse transform and the symmetry of their arithmetic are utilized in the processor. 2D transform is implemented by using duplicated 1D transform. Parallel register array are used to realize the transpose operation. Under (0.35 μm) technology, the gate count is only (3 524) when the frequency is more than (120 MHz).

关 键 词：MPEG-4 视频编码 正整数变换 逆整数变换 并行结构 

分 类 号：TN492[电子电信—微电子学与固体电子学]