测试与可测试性设计发展的挑战  

Challenges for Progress in Test and Design for Testability

作　　者：张永光[1] 徐元欣[1] 王匡[1] 

机构地区：[1]浙江大学信息与通信工程研究所,杭州310027

出　　处：《半导体技术》2005年第2期33-37,共5页Semiconductor Technology

摘　　要：CMOS器件进入超深亚微米阶段,集成电路(IC)继续向高集成度、高速度、低功耗发展,使得IC在测试和可测试性设计上都面临新的挑战。本文首先介绍了测试和可测试性设计的概念,分析了测试和可测试性设计面临的困境;然后讨论了系统芯片设计中的测试和可测试性设计,最后对测试和可测试性设计的未来发展方向进行了展望。CMOS device dimensions scale down to the very deep submicrometer. ICs are going towards higher density, higher speed and lower power dissipation, making new challenges on IC test and design for test. The idea of test and design for testability is discussed, the challenges of test and design for testability are analyzed, then the test and design for testability in SOC design are discussed. The progresses in test and design for testability are put forward.

关 键 词：可测试性设计 可控制性 可观察性 系统芯片 

分 类 号：TN304.07[电子电信—物理电子学]