高速CMOS预放大-锁存比较器设计  

Design of a High Speed CMOS Preamplifier-Latch Comparator

作　　者：宁宁[1] 于奇[1] 王向展[1] 任雪刚 李竞春[1] 唐林[1] 梅丁蕾[1] 杨谟华[1] 

机构地区：[1]电子科技大学微电子与固体电子学院,四川成都610054 [2]上海力通微电子有限公司,上海200233

出　　处：《微电子学》2005年第1期56-58,62,共4页Microelectronics

基　　金：国家自然科学基金项目(60072004)模拟集成电路国家重点实验室基金资助项目(51439010303DZ0221)

摘　　要：基于预放大-锁存理论,提出了一种带1级预放大器的高速CMOS锁存比较器电路拓扑 结构;阐述了其传输延迟时间、回馈噪声和输入失调电压的改进方法。采用典型的0.35μm／3.3 V 硅CMOS工艺模型,通过Cadence进行模拟验证,得到其传输延迟时间380 ps,失调电压6.8 mV, 回馈噪声对输入信号产生的毛刺峰峰值500μV,功耗612μW。该电路的失调电压和回馈噪声与带 两级(或两级以上)CMOS预放大锁存比较器的指标相近,且明显优于锁存比较器。其功耗和传输 延迟时间介于两种比较器之间。该电路可用于高速A／D转换器模块与IP核设计。Based on preamplifier-latch theory, a topology structure of CMOS positive feedback comparator circuit with preamplifier is presented, and methods to improve transmit delay time,kick-back noise and input offset voltage of the circuit are described. Based on standard 0. 35 μm/3. 3 V silicon CMOS process model, the device is simulated with Cadence EDA software. Simulation shows that the circuit has a propagation delay time of 380 ps, an offset voltage of 6. 8 mV, a kick-back noise induced input signal glitch of 500 μV, and a power dissipation of 612 μW. The value of of fset voltage and kick-back noise of the circuit approaches to CMOS preamplifier-latches with two- or multi-stage preamplifier, and evidently less than CMOS latch comparator with positive feedback. Its power dissipation and propagation delay time are a tradeoff of the two comparators. The circuit is applicable for high-speed A/D converter modules and IP core design.

关 键 词：预放大锁存器 锁存比较器 高速比较器 传输延迟 回馈噪声 

分 类 号：TN432.1[电子电信—微电子学与固体电子学]