高速RS(31,15)编译码器的FPGA实现  

Implementation of RS(31,15) Encoder and Decoder with FPGA

作　　者：倪燕[1] 陈颖[1] 杨云志[1] 陈正霞[2] 

机构地区：[1]中国西南电子技术研究所,四川成都610036 [2]成都市中级人民法院,四川成都610041

出　　处：《电讯技术》2005年第1期174-177,共4页Telecommunication Engineering

摘　　要：RS码由于具有优良的纠错能力而得到广泛应用。在军事通信中常以RS(31, 15)作为首选码。本文用一片现场可编程门阵列 (FPGA)芯片实现了高速RS(31, 15)编译码器。该编译码器具有体积小、性能稳定、工作速度高等优点。RS(Reed-Solomon)code is being used widely because of its powerful error correction capability. RS(31,15) code is used first in military communication.This paper has fulfilled RS(31,15) encoder and decoder by means of advanced FPGA(Field Programmable Gate Array). The encoder and decoder have such advantages as small size,good performance and high speed.

关 键 词：RS(31 15)编译码器 纠错 现场可编程门阵列 性能 

分 类 号：TN76[电子电信—电路与系统]