一种基于SOC应用的Rail-to-Rail运算放大器IP核  

A rail-to-rail operational amplifier IP core for SOC application

作　　者：翟艳[1] 杨银堂[1] 朱樟明[1] 王帆[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件教育部重点实验室,陕西西安710071

出　　处：《西安电子科技大学学报》2005年第1期112-115,共4页Journal of Xidian University

基　　金：国家部委预研基金资助项目(51408010601DZ01)

摘　　要：采用上华0 6μmDPDMCMOS工艺,设计实现了一种基于片上系统应用的低功耗、高增益Rail to Rail运算放大器IP核.基于BSIM3V3Spice模型,采用Hspice对整个电路进行仿真,在5V的单电源电压工作条件下,直流开环增益达到107 8dB,相位裕度为62 4°,单位增益带宽为4 3MHz,功耗只有0 34mW.Based on SOC application, a Rail-to-Rail operational amplifier IP core with a low-power and a high gain is presented. The operational amplifier will be realized in the CSMC 0.6μm DPDM CMOS process. The whole circuit is simulated with the BSIM3V3 Spice model in Hspice. With a single power supply of 5V in simulation, it is shown that the Rail-to-Rail operational amplifier has an open loop gan of 107.8dB, a phase margin of 62.4 degrees and a unit gain bandwidth of 4.3MHz, with the static power dissipation being only 0.34mW.

关 键 词：RAIL-TO-RAIL CMOS 运算放大器 IP核 片上系统 

分 类 号：TN402[电子电信—微电子学与固体电子学]