A buffer planning algorithm for chip-level floorplanning  

作　　者：CHENSong HONGXianlong DONGSheqin MAYuchun CAIYici Chung-KuanCheng JunGu 

机构地区：[1]DepartmentofComputerScienceandTechnology,TsinghuaUniversity,Beijing100084,China [2]DepartmentofComputerScienceandEngineering,UniversityofCalifornia,SanDiego,USA [3]DepartmentofComputerScience,Science&TechnologyUniversityofHongKong,China

出　　处：《Science in China(Series F)》2004年第6期763-776,共14页中国科学（F辑英文版）

摘　　要：This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.

关 键 词：buffer planning dead space REDISTRIBUTION FLOORPLANNING VLSI corner block list. 

分 类 号：TN47[电子电信—微电子学与固体电子学]