Automated floorplanning or space layout planning has been a long-standing NP-hard problem in the field of computer-aided design,with applications in integrated circuits,architecture,urbanism,and operational research.I...
supported by the National Natural Science Foundation of China(Nos.61403174 and 61503165);the Natural Science Foundation of the Jiangsu Higher Education Institutions of China(No.14KJB 520011);the Jiangsu Provincial Science Foundation for Youths(No.BK20150239)
Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed...
The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extend...
This work is supported by the National Natural Science Foundation of China (No.90207001, No.60506010) and National 863 Project of China (No.2004AA1Z1050, No.2005AA1Z1230).
As power density increases steadily, temperature has become an important design concern. One of the most effective ways to reduce chip peak temperature is thermal-aware fioorplanning, in which thermal analysis has to ...
This work is supported by the National Natural Science Foundation of China (Grant Nos. 60473126 and 90407005), National Natural Science Foundation of China and Hong Kong RGC Joint Project (Grant No. 60218004) and the Hi-Tech Research & Development 863 Program of China (Grant Nos. 2004AA1Z1050 and 2002AA1Z1460).
With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List (CBL), we prop...
We present a deterministic algorithm for large-scale VLSI module placement. Following the less flexibility first (LFF) principle,we simulate a manual packing process in which the concept of placement by stages is in...
We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning...
We develop a 3D bounded slice-surface grid (3D-BSSG) structure for representation and introduce the solution space smoothing technique to search for the optimal solution. Experiment results demonstrate that a 3D-BSS...
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provid...
This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. I...