Design and Verification of High-Speed VLSI Physical Design  

作　　者：DianZhou Rui-MingLi 

机构地区：[1]DepartmentofElectricalEngineering,TheUniversityofTexasatDallas,Richardson,TX75083-0688,U.S.A.／／SchoolofMicroelectronics,FudanUniversity,Shanghai200433,P.R.China [2]DepartmentofElectricalEngineering,TheUniversityofTexasatDallas,Richardson,TX75083-0688,U.S.A.

出　　处：《Journal of Computer Science & Technology》2005年第2期147-165,共19页计算机科学技术学报（英文版）

摘　　要：With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.

关 键 词：VLSI physical design floorplanning and placement INTERCONNECT delay wire sizing buffer insertion power order reduction power grid parameter extraction clock distribution 

分 类 号：TN405[电子电信—微电子学与固体电子学]