VSP中的变字长解码器设计研究  

Research on design of variable length decoder in video signal processor

作　　者：毛讯[1] 姚庆栋[1] 虞露[1] 

机构地区：[1]浙江大学信息与电子工程系,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2001年第6期583-587,共5页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目 (6 9972 0 43)

摘　　要：提出了视频信号处理器中的变长解码器核设计 .采用基于 PLA的并行算法 ,在 PL A中存储了以编码码字为输入 ,码值和码长为输出的各个变长码真值表 .用从 PL A中查出的码长来控制桶形移位器的位移 ,实现每个周期解出一个码字 . VLD采用了数据驱动原理 ,并在任务分配方面进行了调整 ,以适应 VSP进行任务流水的总体要求 .The design of VLD (variable length decoder) core with parallel algorithm based on PLA (programmable logic array) was presented. Each Variable Length Code truth-table of which the input is the bit stream code and the output is the value and length of the code is stored into different PLA respectively. The PLA's output code length controls the barrel shifter to eject the right number of bits from the bit stream, and one variable length code can be decoded in each clock cycle. Because the decoding time varies with the different VLD streams, the decoder's control strategy is implemented with the data drive principle and adjusted to balance task assignment to realize the task level pipeline required by VSP. Compared with conventional method, the proposed method in this paper is featured with high parallel processing speed and less hardware requirement by using PLA. So it can be implemented in VLSI (very large scale integration).

关 键 词：MPEG-2 变字长解码 视频解码 

分 类 号：TN919.8[电子电信—通信与信息系统]