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机构地区:[1]兰州大学物理科学与技术学院静电感应器件研究所,兰州730000
出 处:《Journal of Semiconductors》2005年第2期258-265,共8页半导体学报(英文版)
摘 要:A cylindrical gates model of the static induction transistor is proposed and mirror method is used to calculate the distribution of electric potential.The results show that:the potential barrier is directly determined by channel over pinched-off factor;gate efficiency η decreases as the gate dimension α 2 and shifted gate voltage are minished,and what differs from the first-order theory is that η will tend to zero at the shifted gate voltage tends to zero when V D=0;at low current,the voltage amplification factor μ increases as the drain current rising.When the drain current reaches certain degree,the voltage amplification factor keeps almost constant.In the end,an analytical description of SIT’s characteristic suited to both triode-like and mixed I-V characteristics are obtained.The predicted I-V curves are consistent perfectly with the reported experimental ones.针对埋栅型静电感应晶体管 (SIT)提出一种柱栅模型 .用镜像法计算了器件内电势分布 ,并在此基础上计算了沟道势垒、栅效率、电压放大因子等 .结果表明 :沟道势垒直接取决于沟道过夹断因子 ;栅效率随栅尺寸和位移栅压的减小而减小 ,并随位移栅压一起趋向于 0 ;在小电流情况下电压放大因子随电流的增大而增大 ,到一定数值后 ,电压放大因子趋于常数 .最后给出了SITI V特性解析表达式 ,它既适用于类三极管特性 (加大栅压下 )也适用于混合特性 (较小栅压下 ) ,且由此得到的I V特性曲线和实验符合较好 .
关 键 词:static induction transistor mirror method I-V characteristic
分 类 号:TN32[电子电信—物理电子学]
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