1.8V千兆以太网收发器低抖动时钟电路  

A 1.8 V Low-jitter Clock Generator for 1000 Base-T Ethernet Transceiver

作　　者：陆平[1] 王彦[1] 李联[1] 郑增钰[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《复旦学报（自然科学版）》2005年第1期155-160,共6页Journal of Fudan University：Natural Science

摘　　要：采用新型的高速鉴频鉴相器(TSPC)、典型的抗抖动的电荷泵和对称负载差分延迟单元,设计了0.18μm标准CMOS工艺、1.8V工作电压的锁相环,经过系统稳定性验证和spice仿真,125MHz的最大时钟输出在(75℃@TT)情况下,具有±3σ=70ps左右的long term低抖动.同时,在3种不同工艺下施加0.1Vpeak peak正弦电源噪声时,对电路的工作情况进行了仿真,均能很好满足电路设计的要求(对于1000Base T,Δt=8ns/16=500ps,根据时钟恢复算法的仿真,较严格peak peak抖动要求约为(2%～3%)×baud=160～240ps).The key of 1000 Base-T Ethernet frequency synthesizer is a charge-pump phase locked loop. The PLL is designed with a new high speed phase and frequency detector (TSPC),a low-power noise-suppressed charge pump and typical symmetrical-load differential delay cells PLL,which makes the circuit work stably. Meanwhile,the circuit has small clock jitter under different temperatures and process conditions. System stability verification and spice simulation show the 125 MHz output clock is about 70 ps (75 ℃ @ TT).For three different process conditions the circuit can also meet the specification perfectly with 0.1 V_(P-P) noise supply.(In 1000 Base-T, Δt=8 ns/16=500 ps.According to the CDR algorithm,more strict requirement of jitter_(peak-peak) is about (2%-3%)×baud=160-240 ps). The power supply is (1.8 V) and 0.18 μs standard CMOS technology is adopted.

关 键 词：时钟电路 收发器 抗抖动 SPICE仿真 鉴频鉴相器 电源噪声 时钟恢复 千兆以太网 复算 时钟输出 

分 类 号：N941[自然科学总论—系统科学] TP393[自动化与计算机技术—计算机应用技术]