USB2.0接口IP核的开发与设计  

The Design and Development of USB 2.0 Interface IP Core

作　　者：阮利华[1] 王祥[1] 黄全平[2] 周荣政[2] 洪志良[2] 蒋凤仙[1] 

机构地区：[1]复旦大学通信科学与工程系,上海200433 [2]复旦大学微电子学系,上海200433

出　　处：《复旦学报（自然科学版）》2005年第1期173-177,共5页Journal of Fudan University：Natural Science

基　　金：国家863专项资助项目(2002AAIZ1450);上海市科委SDC资助项目(037062017)

摘　　要：介绍了一种基于USB2.0协议的设备接口的IP核设计.着重研究了USB2.0协议控制器、缓存控制器、工作模式控制等硬件数字电路的实现,该电路支持高速(480Mbps)和全速(12Mbps)传输.为了满足USB2.0高速的传输要求,减小硬件设计的复杂性和硬件开销,整个系统采用硬件电路和MCU固件结合的方法进行设计,同时使用了不同传输方式缓冲区共用的双缓冲区缓存结构,因此电路具有实现简单,硬件开销小,传输速度较高等优点.设计的电路已经通过FPGA验证.An IP core design of USB 2.0 interface is presented. The stress is put on the digital circuit implementation of USB 2.0 Protocol Controller, Buffer Controller and Work Mode Controller. The circuit can operate at both USB high-speed (480 Mbps) and full-speed (12 Mbps) rates. In order to achieve high-speed transaction request of (USB 2.0) and reduce the design complexity of the hardware, a structure of combining MCU firmware and hardware is proposed. A double-buffered structure is adopted in the design to reduce the hardware cost. The proposed structure of USB 2.0 interface has been verified with FPGA.

关 键 词：USB2.0协议 缓存 USB2.0接口 硬件 固件 IP核设计 开销 FPGA验证 数字电路 传输方式 

分 类 号：N941[自然科学总论—系统科学] TP333[自动化与计算机技术—计算机系统结构]