一种40 ns 16 kb EEPROM的设计与实现  

Design and Implementation of a 40-ns 16-kb EEPROM

作　　者：徐飞[1] 贺祥庆[1] 张莉[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《微电子学》2005年第2期133-137,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60236020)

摘　　要：　基于0.35μmCMOS工艺,设计并实现了一个3.3V16kbEEPROM存储器。该电路采用2k×8的并行结构体系。通过优化设计灵敏放大器、位线译码和字线充放电等电路,加快了读取速度,典型值仅40ns;通过编程模式和编程电路的设计,提高了编程速度,页编程时间为2ms,等效于每字节62ms。重点研究了片上高压产生电路,提出了一种在不增加工艺难度和设计复杂度的情况下提供良好性能的电荷泵电路。电路的单元面积为11.27μm2,芯片尺寸约1.5mm2。A 2 k×8 bits EEPROM based on 0.35 μm CMOS process is developed, which operates from a single 3.3 V power supply. Several design techniques are summarized. An improved readout circuit consisting of sensing amplifier (SA), bit-line decoding and word-line charge/discharge circuit to minimize the access time is described in particular, along with the approach to optimizing the programming operation. Emphasis is made on the on-chip high-voltage generation circuit, and a zero threshold voltage charge pump is proposed, which can improve the performance without additional design and process complexity. A 40 ns typical access time and 2 ms page programming time are achieved. The cell size is 11.27 μm^2 and chip size is about 1.5 mm^2.

关 键 词：EEPROM 存储器 电荷泵 灵敏放大器 并行编程 

分 类 号：TN402[电子电信—微电子学与固体电子学]