针对线间串扰现象的静态定时分析  

Static Timing Analysis for the Line-to-Line Crosstalk Phenomenon

作　　者：沈培福[1,2] 李华伟[1] 

机构地区：[1]中国科学院计算技术研究所信息网络实验室 [2]北京师范大学计算机科学与技术系,北京100875

出　　处：《计算机工程与科学》2005年第4期25-28,53,共5页Computer Engineering & Science

基　　金：国家自然科学基金项目(90207002;60242001);中科院计算所基础研究基金(20036160)

摘　　要：超深亚微米工艺下,线间串扰是导致电路故障的主要原因之一。尽管可能导致故障的线间串扰的数量巨大,但真正会引起故障的线间串扰却相对较少。因此,如果能在对电路验证或测试前进行静态定时分析,找出那些导致电路故障的线间串扰,则可以有效提高测试生成效率,并降低测试成本。基于此目的,文章在静态定时分析中引入对线间串扰现象的分析,在线时延模型的基础上使用重叠跳变对故障模型,只需要求出与最长通路的重叠跳变对即可。在对 ISCAS'89基准电路的实验中,各电路需要测试的串扰数平均减少至 10%以下。相对于已发表的实验结果,本文的实验结果具有较高的CPU效率。Current design trends show that crosstalk issues in deep sub-micron can cause severe problems of design validation and test. Although the number of all possible crosstalks that may cause faults is huge, the number of those that really cause faults is much smaller. So, the efficiency of test generation can be improved if the static timing analysis (STA) is done before it. In this paper, we introduce the analysis of crosstalk into the STA process. The overlapped transition pairs fault model is used based on the line delay model. Only transitions overlapped with the longest paths are considered during faults selection. Experimental results for the ISCAS'89 benchmark circuits show that the number of faults is reduced significantly to less than 10% of the original number of candidates. The CPU efficiency of our experimental results is better than that of the previous work.

关 键 词：集成电路 制造工艺 超深亚微米工艺 线间串扰现象 静态定时分析 

分 类 号：TM405[电气工程—电器]