一款低功耗SoC芯片的时钟管理策略  

Clock Management Strategy of a Low-power SoC Chip

作　　者：戴红卫[1] 郭炜[1] 韩泽耀 王琴[1] 

机构地区：[1]上海交通大学微电子学院,上海200030

出　　处：《微电子学与计算机》2005年第3期32-35,共4页Microelectronics & Computer

摘　　要：文章提出一种系统级和RTL级协同设计的时钟管理策略,显著地降低了时钟网络的动态功耗,弥补了现有工具只能在设计后期才能发挥作用的不足,达到降低整个SoC芯片功耗的目的;同时,分析该方案实现中可能存在的问题,并给出解决方案。This paper presents a clock management strategy for a low power SoC, which achieves the goal of total power dissipation reduction of the chip. The strategy remarkably reduces the dynamic power dissipation of the clock network, and is the complement of current tools that can only act in the latter stage of designing. Meanwhile, this paper analyzes the problems met in implementation, and give solutions to these problems.

关 键 词：协同设计 时钟网络 功耗 

分 类 号：TN4[电子电信—微电子学与固体电子学]