SoC嵌入式flash存储器的内建自测试设计  

Embedded Flash Memory BIST For System-on-a-Chip

作　　者：鉴海防[1] 王占和[1] 李印增[1] 张昭勇 

机构地区：[1]北京理工大学微电子研究所,北京100081 [2]世宏科技(苏州)有限公司,江苏苏州215021

出　　处：《微电子学与计算机》2005年第4期87-91,共5页Microelectronics & Computer

摘　　要：深亚微米技术背景下,嵌入式存储器在片上系统芯片(system-on-a-chip,SoC)中占有越来越多的芯片面积,嵌入式存储器的测试正面临诸多新的挑战。本文论述了两种适合SoC芯片中嵌入式flash存储器的内建自测试设计方案。详细讨论了专用硬件方式内建自测试的设计及其实现,并且提出了一种新型的软硬协同方式的内建自测试设计。这种新型的测试方案目标在于结合专用硬件方式内建自测试方案并有效利用SoC芯片上现有的资源,以保证满足测试过程中的功耗限制,同时在测试时间和芯片面积占用及性能之间寻求平衡。最后对两种方案的优缺点进行了分析对比。Embedded memories consume an increasing portion of the die area in deep submicron system-on-a-chip (SoC). New challenges now confronted the test of embedded memories. In this paper we present two BIST approaches suitable for embedded flash memory testing in a SoC environment. The hardware-centric approaches for embedded memory is examined and a new built-in self-test(BIST)-based method called hardware/software co-testing is introduced. This novel approach aims to balance the usage of the existing on-chip resources and dedicated hardware-centric approach such that the functional power constraints are not exceeded during test while trading-off the testing time against DFT area and performance overhead. The advantages and disadvantages of these two methods are compared in the end.

关 键 词：片上系统 嵌入式flash存储器 内建自测试 封装器 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]