An Asynchronous Implementation of Add-Compare-Select Processor for Communication Systems  

一种适用于通讯系统的异步加-选择-比较器(英文)

作　　者：赵冰[1] 仇玉林[1] 吕铁良[1] 黑勇[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《Journal of Semiconductors》2005年第5期886-892,共7页半导体学报（英文版）

基　　金：国家自然科学基金资助项目(批准号:60076017,90307004)~~

摘　　要：A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous comparator unit,and asynchronous selector unit are proposed.A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process.At a supply voltage of 5V,when it operates at 20MHz,the power consumption is 75.5mW.The processor has no dynamic power consumption when it awaits an opportunity in sleep mode.The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19.18ns is only 82% of the worst-case response time 23.37ns.Compared with the synchronous 4-bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.介绍了一种适用于Viterbi解码器的异步ACS(加法器比较器选择器)的设计.它采用异步握手信号取代了同步电路中的整体时钟.给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路.采用全定制设计方法设计了一个异步4 -bit ACS,并通过0 .6μm CMOS工艺进行投片验证.经过测试,芯片在工作电压5V,工作频率20MHz时的功耗为75. 5mW.由于采用异步控制,芯片在“睡眠”状态待机时不消耗动态功耗.芯片的平均响应时间为19 .18ns,仅为最差响应时间23 .37ns的82%.通过与相同工艺下的同步4 -bit ACS在功耗和性能方面仿真结果的比较,可见异步ACS较同步ACS具有优势.

关 键 词：asynchronous circuits Viterbi decoder ACS response time 

分 类 号：TN76[电子电信—电路与系统]