基于高速时钟电路终端的信号完整性分析  

Signal Integrity Analysis Based on Terminal of High-Speed Clock Circuit

作　　者：陈倩[1] 

机构地区：[1]四川大学电子信息学院,四川成都610064

出　　处：《电讯技术》2005年第3期185-188,共4页Telecommunication Engineering

摘　　要：本文分析了高速时钟电路的终端在确保信号完整性方面的重要作用,介绍了几种常用的终端方法,并用软件对采用上述终端方法的具体电路进行了仿真,最后从工程实现的角度选用了一种适宜的终端方法,得到了实测结果。The important function of high-speed clock circuit terminal in ensuring signal integrity is analysed and several often-used terminal methods are introduced. Also, specific circuits adopting above terminal methods are simulated with professional software. Finally, from the view of engineering and with connection to practical application,a hardware circuit is designed, and the experiment data are obtained.

关 键 词：高速时钟电路 终端 信号完整性 分析 

分 类 号：TN702[电子电信—电路与系统]