折叠内插模数转换器分析及实现  

Analysis and Implementation of a Folding/Interpolating ADC

作　　者：陈诚[1] 毛静文[1] 王照钢[1] 任俊彦[1] 闵昊[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《Journal of Semiconductors》2005年第6期1234-1238,共5页半导体学报（英文版）

基　　金：国家高技术研究发展计划(批准号:2002AA1Z1360);上海市集成电路设计创新(批准号:027062024;027062005)资助项目~~

摘　　要：应用Matlab/Simulink工具对折叠内插模数转换器进行了建模,研究了具有8bit分辨率、200MHz采样频率的该模数转换器的芯片设计和实现.系统设计时采用Matlab/Simulink进行行为级建模并分别分析了预放大的增益、折叠电路的带宽以及比较器的失调对动态性能的影响.设计实现的模数转换器实测结果表明,积分非线性误差和微分非线性误差分别小于0.77和0.6LSB,在采样频率为200MHz及输入信号频率为4MHz时,信号与噪声及谐波失真比为43.7dB.电路采用标准0.18μmCMOS数字工艺实现,电源电压为3.3V,功耗181mW,芯核面积0.25mm2.Modeling and analysis with Matlab/Simulink and chip implementation for a 8bit 200Ms/s folding/interpolating analog-to-digital converter (ADC) are described.During system design,a behavioral model is built in Matlab/Simulink.The sensitivity of dynamic performance with the gain of pre-amplifier,the bandwidth of folder,and the offset of comparator are analyzed.The ADC is designed and implemented according to the analysis.An INL/DNL of 0.77LSB/0.6LSB is measured.An SNDR figure of 43.7dB is achieved at 4MHz input frequency when operated at full speed.The chip is realized in a standard digital 0.18μm CMOS technology and consumes a total power of 181mW from a 3.3V power supply.The active area is 0.25mm2.

关 键 词：模数转换器 电路建模 折叠内插 

分 类 号：TN792[电子电信—电路与系统]