适用于H.264视频解码器的VLD设计  

Design of Variable Length Decoder for H.264 Video Decoder

作　　者：戴春泉[1] 李锦涛[1] 黄晁[1] 

机构地区：[1]中国科学院计算技术研究所,北京100080

出　　处：《计算机工程》2005年第13期162-164,共3页Computer Engineering

基　　金：国家"863"计划基金资助项目(2001AA110342)

摘　　要：设计了一种适合于H.264的变字长解码器,根据码流特点进行模块划分,减少硬件开销;采用并行结构解NAL包,解码效率高;采用了桶形移位器,进行并行解码,每个时钟解一个码字。采用Verilog语言进行设计、仿真,并通过了FPGA验证,可以在FPGA上实时解码标准清晰度的H.264视频。用0.18μmCMOS工艺库作综合,电路规模为1.6万门左右,最高频率能够达到150MHz。This paper proposes an implementation of variable length decoder for H.264. The design is separated into several parts according to the specialty of the code flow so that the hardware cost can be decreased. The NAL packet is decoded by parallel structure module to get the high decoding efficiency. The barrel-shifters which are based on parallel structure can decode one code in every cycle. The module is designed, simulated based on Verilog HDL. The whole design has been verified by FPGA. The FPGA system can decode the standard-definition H.264 video in real-time. The design consists of 16 k gates when synthesized based on 0.18 μm CMOS library. The highest frequency can reach 150 MHz.

关 键 词：专用集成电路 视频解码 变字长解码 H.264 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术]