一种基于FBMA算法的整像素运动估计芯片的VLSI设计  

VLSI Design for Full-Search Block-Matching Full-Pel Motion Estimation Processor

作　　者：何卫锋[1] 毛志刚[1] 吕志强[1] 尹海丰[1] 

机构地区：[1]哈尔滨工业大学微电子科学与技术系,哈尔滨150001

出　　处：《计算机研究与发展》2005年第7期1225-1230,共6页Journal of Computer Research and Development

摘　　要：给出了一种基于全搜索块匹配算法的运动估计电路的改进结构,并完成了VLSI设计.通过采用多端口匹配策略和双时钟方案,使得在提高先前帧搜索区域像素数据重复利用率的同时,将脉动阵列的计算效率提高到74.9%.采用TSMC0.25μm1P5MCMOS工艺,完成了运动估计芯片的VLSI实现,其芯片面积为3.37mm×3.37mm,最高工作频率为110MHz.综合后仿真表明在89.4MHz的频率下,该电路可以对支持MPEG4ASProfile标准的ITUR601格式视频图像(720×480@30HzNTSC或720×576@25HzPAL)进行基于整像素的实时运动估计.An improved architecture for motion estimation using the full-search block-matching algorithm is proposed in this paper. To reduce the utilization of the global bus to the external memory and to improve the data reuse efficiency of search frame pixels, a multi-port matching scheme and double clock strategy are adopted. Compared with the previous FBMA architecture, this new architecture achieves 74.9% processor utilization as well as improves the reuse efficiency of search area pixel data. The motion estimation processor is implemented using the TSMC 0.25μm 1-poly 5-metal CMOS technology, which occupies a silicon area of 3.37mm×3.37mm and operates at 110MHz. Experimental results show that it is able to estimate full pixel motion vectors of MPEG-4 AS profile sequences in ITU-R601 format (720×480@30Hz?NTSC or 720×576@25Hz?PAL) in real-time at around 89.4MHz

关 键 词：全搜索块匹配算法 脉动阵列 运动估计 超大规模集成电路 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]