多DSP处理器HOST接口的硬件设计  

The Host Interface Design of Multi-DSP Processor

作　　者：季晓燕[1] 江鹏[2] 蔡慧智[2] 

机构地区：[1]中船重工717研究所,430074 [2]中国科学院声学研究所,100080

出　　处：《国外电子测量技术》2005年第8期29-33,共5页Foreign Electronic Measurement Technology

摘　　要：在现代通信、雷达和声纳系统中,需要进行非常复杂的数据处理。目前解决这些问题的有效办法是将多个DSP组成阵列处理系统,以增加整体数据处理能力。针对系统的要求,采用基于CPCI的高速阵列信号处理板卡。该板选用AD公司的高性能浮点DSP处理器TigerSharc101,使整板具有14.4GFLOPS的峰值浮点运算能力,它提供LinkPort来实现片间和板间通信。本文介绍了该板的原理框图,FPGA的实现结构,着重于Host接口逻辑设计。实践证明,该板具有超强的运算能力和良好的扩展性。In the modern communication, sonar and radar systems, we need to process huge data.One of the effective ways to solve this problem is to build a system with multiprocessor, so that the processing ability can be enhanced. According to the demands of the system, we have designed a high speed array signal processing board which is based on CPCI structure. We choose the TigerSharcl01 as the core processor, whose peak processing ability is 14.4GFLOPS. The board has link ports to realize the communication between TS101 and boards. In this paper, we introduce the base structure of the board and FPGA design and emphasize on the host interface design. Our applications showed that the board has a great processing ability and expansibility.

关 键 词：CPCI总线 阵列信号处理 TigerSharc101 DSP处理器 硬件设计 HOST 接口 数据处理能力 现代通信 声纳系统 

分 类 号：TN911.72[电子电信—通信与信息系统] TP368.1[电子电信—信息与通信工程]